1. Field of the Invention
This invention relates to processors for voice band telecommunications and more particularly to digital processors which have the capability of processing code excited linear predictive algorithms.
2. Discussion of Related Art
Recently, cellular telephone systems have become more practical and popular. Their popularity has increased to the point where service availability will soon be unable to meet demand. It has therefore been proposed to implement a digital cellular network which incorporates predictive speech signal coding for reducing the bandwidth of transmitted speech thereby enhancing system performance and enabling time division multiplexing which significantly increases user availability.
The Telecommunication Industries Association has adopted a standard, Digital Cellular Standard IS-54, which implements a vector sum excited linear predictive (VSELP) vocoder algorithm for use in the United States. This algorithm is computationally intensive, requiring on the order of 6.45.times.10.sup.6 arithmetic operations per second and 15.6 million instructions per second (MIPS).
Other areas of the world are also moving toward digital cellular systems. Japan has recently adopted a VSELP algorithm similar to the United States, and Europe is moving toward a CELP algorithm referred to as Group Special Mobile (GSM).
Currently, digital signal processors (DSPs) such as the DSP65000 family manufactured by Motorola, Inc. are available for implementing digital algorithms such as digital filters, fast fourier transforms, correlation functions, etc. Such processors have special features such as modulo addressing, hardware DO loops, 24-bit by 24-bit hardware multipliers, etc. to facilitate the large number of high precision arithmetic operations required in digital signal processing. DSPs are ideally suited for executing the VSELP and similar algorithms except that current models have too low a clock rate. The DSP65000 family, for example has a nominal clock rate of 20.48 MHz giving an execution rate of 10.24 MIPS. This can be increased to 27 MHz for an execution rate of 13.5 MIPS. To accommodate the 15.6 MIPS needed for IS-54, the clock rate would have to be increase to about 32 MHz. Such an increase would require redesign of the DSP.